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ATmega128
Performing Page
Erase by SPM
To execute page erase, set up the address in the Z-pointer and RAMPZ, write “X0000011” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and
R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the
Z-pointer must be written zero during this operation.
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Page Erase to the R WW section: The NR WW section can be read during the page erase.
Page Erase to the NR WW section: The CPU is halted during the operation.
Filling the Temporary
Buffer (Page Loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The
content of PC W ORD in the Z-register is used to address the data in the temporary buffer. The
temporary buffer will auto-erase after a page write operation or by writing the R WW SRE bit in
SPMCSR. It is also erased after a System Reset. Note that it is not possible to write more than
one time to each address without erasing the temporary buffer.
Note:
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.
Performing a Page
Write
To execute page write, set up the address in the Z-pointer and RAMPZ, write “X0000101” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and
R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must
be written zero during this operation.
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Page W rite to the R WW section: The NR WW section can be read during the page write.
Page W rite to the NR WW section: The CPU is halted during the operation.
Using the SPM
Interrupt
Consideration While
Updating BLS
Prevent Reading the
RWW Section During
Self-Programming
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling
the SPMCSR Register in software. W hen using the SPM interrupt, the interrupt vectors should
be moved to the BLS section to avoid that an interrupt is accessing the R WW section when it is
blocked for reading. How to move the interrupts is described in “Interrupts” on page 59 .
Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
During Self-Programming (either page erase or page write), the R WW section is always blocked
for reading. The user software itself must prevent that this section is addressed during the Self-
Programming operation. The R WW SB in the SPMCSR will be set as long as the R WW section is
busy. During Self-Programming the interrupt vector table should be moved to the BLS as
described in “Interrupts” on page 59 , or the interrupts must be disabled. Before addressing the
R WW section after the programming is completed, the user software must clear the R WW SB by
writing the R WW SRE. See “Simple Assembly Code Example for a Boot Loader” on page 282 for
an example.
280
2467X–AVR–06/11
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